Apollo Investigation
Was the Apollo Computer flawed?

Apollo Guidance Computer Memory Update

by Aerospace Engineer Xavier Pascal
 

Note: the images in this article are not optimised for cell phones
The original report is available here

Introduction

The AGC had a 16-bit word length with 15 data bits and one parity bit. Most of the software on the AGC was stored in a ROM known as core rope memory.

This report update is based on NASA’s published drawings and documentation. These official drawings describe the Apollo Guidance Computer (AGC) in full detail – there are no other existing schematics. These documents reveal design problems which cannot be explained or excused even for purposes of simplification. For example, on the secondary side of the transformer that transmits the pulse from the selection circuit to the bit amplifier there should be an RC circuit responsible for transforming the pulse (which is very short) into a temporary one, allowing the logic to read it – but this is absent in the description of the AGC memory.

Such an omission would prevent the memory logic from working. There are numerous other reasons for this memory not to work, each of them individually is sufficient to prevent the memory from working correctly. No doubt, as with anomalies in the Apollo imagery, the NASA design engineers and technical writers were hoping that at some point these matters would be exposed.

The Apollo record is that the AGC served on the Earth-orbital missions, the six lunar landing missions, the three Skylab missions, and the Apollo-Soyuz test project.

How did the Apollo core rope memory actually work?

Fig 1

The AGC cores are located at the intersection of rows and columns of a matrix of wires; there are two perpendicular wires going through each core. The magnetic field of the core can be modified if each of the wires crossing inside it is fed with a half current – these two half currents sum to the full current which allows the magnetic field of that core to be modified. But if only one wire is fed with a half current and not the other, this half current alone is not enough to change the magnetic field of the core.

Only the central core on the schematic is crossed with two wires fed with a half current, and it is the only one which will have its magnetic field modified. The other cores have only one wire fed with a half current and the other wire has no current passing through it, so their magnetic field will not be modified. This process allows the specific targeting of the core which is to be modified (or read).

Fig 2

When the two intersecting wires are fed with a negative current, the ferrite core is polarized negatively. Conversely, when the two crossing wires are fed with a positive current, the ferrite core is polarized positively. The fact that the ferrite core is polarized negatively corresponds to a bit set to zero, and the fact that it is polarized positively corresponds to a bit set to one.

When the core is polarized negatively, and negative currents are sent through the crossing wires, the magnetic field of the core will remain unchanged; a sense wire which goes through the core will detect nothing; the computer then knows that a zero was stored on this core.

On the other hand, when the core is polarized positively, and negative currents are sent through the crossing wires, the magnetic field of the ferrite core will change, and this change creates a short impulse through the sense wire; though this impulse is very short, the electronics are fast enough to detect it. It is the detection of this impulse which says the ferrite core was polarized positively before the currents were sent through the wires; the computer then knows that a one was stored in this core.

The problem of the reading is that it is always made by sending a negative current through the crossing wires, and thence the core will always be polarized negatively after it has been read, even if it was polarized positively prior to the reading. This means that if an impulse has been detected in the sense wire, positive currents must then be sent through the crossing wires so that the core returns to it previous state corresponding to the one it was memorizing (otherwise, next time a zero is read instead of a one). This may all seem rather complicated but in fact this process is extremely fast and permits reading the memory at quite a high speed.

Fig 3The cores are inserted into an array of wires, and these wires are commanded with circuits in the schematic represented on the right; this circuit can send either a negative current (for reading the cores) or a positive current (for reprogramming the current of the cores that are detected to a one); the negative or positive current will only be sent if an enable signal allows it; this enable signal depends on the current memory address which is to be read or rewritten.

Therefore the principle of the core memory depends on a dynamic change of the magnetic field. When the core memory is switched off, it is always de programmed, and cannot hold information; when it is switched on, the cores must initially be polarised positively or negatively, by sending either positive or negative currents according to whether the cores have to memorize a one or a zero.

When memory data is to be modified, the intersecting wires of the cores corresponding to those of this data must be fed with positive currents (unless they already are positively polarized), and conversely the crossing wires of the cores corresponding to the zeroes of this data must be fed with negative currents (unless they are already negatively polarized).

Fig 4

In a normal core memory, you can see that the activation wires passing through the cores have an important diameter relative to the core. Indeed, they must be able to carry sufficient current to change the magnetic field of the core. If they are too thin, they would not be able to stand this current. In the Wikipedia AGC article, it states that each half current was between 0.4 and 0.8 ampere (two half currents must be sent to change the magnetic field of the core, one is not enough); if it is a single wire which must change the magnetic field of the core, this current must be doubled; it would then be between 0.8 and 1.6 ampere. The sense wires can be thinner as the impulse they get is relatively weak.

Fig 5

So, how did the rope core memory of the Apollo AGC actually work? The sense wires were made to go either through cores or over them; when a sense wire goes through a core, it is supposed to represent a one, and when it is going over instead of going through, it was supposed to represent a zero. Up to 64 sense wires could go through a core. I located a NASA document explaining how the core rope memory of Apollo and the erasable memory worked.

Fig 6

First I offer some explanation about the diode and the transistor, as I'll refer to these explanations in what follows. A diode is a device which lets the current pass in one direction and blocks it in the other direction; and in the direction it lets the current pass, the diode behaves like a resistor of almost null value.

Fig 7

A transistor is a more sophisticated device which has three electrodes called the base (the electrode on the left), the emitter (the electrode with an arrow) and the collector (the top one). The particularity of a transistor is that a small variation between the base and the emitted yields a bigger variation between the collector and the emitter; this particularity allows the transistor to be used as an amplifier. A transistor can also be used to block or allow a current between the collector and the emitter with a command inputted on the base of the transistor.
There are two types of transistors:
– In transistors called "NPN" the current goes from the collector to emitter; these transistors are represented with the arrow of the emitter oriented toward the exterior of the transistor.
– In transistors called "PNP" the current goes from the emitter to the collector; these transistors are represented with the arrow of the emitter oriented toward the interior of the transistor.

Fig 8

When the transistor is connected so that a current can go from the base to the emitter, the current can go from the collector to the emitter (or from the emitter to the collector in the case of a PNP); the transistor if then unblocked.

Fig 9

But when the transistor is connected so that no current can go from the base to the emitter, the current cannot go from the collector to the emitter (or vice versa in the case of a PNP); the transistor is then blocked.

Fig 10

This is the simplified schematic provided to explain how the Apollo core rope memory works. In order to test which cores a sense line is passing through, and which cores it is bypassing, it is not possible to activate several cores at the same time.

Fig 11

Indeed, if two cores a sense line is passing through are activated simultaneously, the sense line will receive an impulse, but it will not be possible to know if the sense line is going through the first of these two cores, or the second one, or both, because whether only the first core generates an impulse, or the second does, or both do, in all these cases the same impulse, standing for a 1, will be generated in the sense wire.

On the other hand, if the sense wire receives no impulse, then it can be sure that it is passing through none of these cores, and so zeroes are programmed on these cores for this sense wire. The only solution to test the bits on a sense line is to activate the cores one at a time (but when a core is activated, all the sense lines can simultaneously be tested for this core).

Fig 12

If only the second core is activated, if a sense line sees an impulse, then it can be sure it is going through this core; and if it sees no impulse, it can be sure it is bypassing this core.

Fig 13

Likewise, if the only the third core is activated, if a sense line sees an impulse, then it can be sure it is going through this core; and if it sees no impulse, it can be sure it is bypassing this core. When successively activating the second core and the third core, the second line receives an impulse in both cases, and it thence knows with certainly it has a 1 programmed on these two cores.

Fig 14

So, how to activate cores independently, so that only one can be activated at a time? The most logical way is to make each activate line pass through a single core, one per core. There are two possible ways:

1) The way described on the upper half of the figure.
A set current (left of the figure) in one direction is first sent into the activate line, changing the magnetic field of the core.
Then a reset current (right on the figure) in the opposite direction is sent into the activate line to reset the magnetic field of the core back to its original state.
This double change of the magnetic field of the core generates an impulse into a sense line which goes through the core (and, if the sense line bypasses the core, it will see no impulse).

2) The way described on the lower half of the figure.
A set current (left of the figure) in one direction is first sent into the activate line, changing the magnetic field of the core.
Then a reset current (right on the figure) in the opposite direction is sent, not into the activate line, but into a common reset line to reset the magnetic field of the core back to its original state.
This double change of the magnetic field of the core also generates an impulse into a sense line which goes through the core.

In this mode, only set currents are sent into the activate lines, and only the common reset line resets the cores.

Fig 15

But, curiously, the designers have not chosen this natural mode to activate the cores. The lines which allow the selection of which core is activated are not "Activate lines", but "Inhibit lines", and they work in a converse way: They don't allow it to activate a core, but on the contrary to prevent the activation of a core. In my examples, the bottom wire going through a core is an inhibit line, the central wire is a common set/reset line which goes through all the cores, and the upper thinner wire is a sense wire.

1) The processes of activation of a core is described on the upper half of the figure.
A set current (left of the figure) in one direction is first sent into the common set/reset line, changing the magnetic field of the core.
Then a reset current (right on the figure) in the opposite direction is sent into the common set/reset line, resetting the magnetic field of the core back to its original state. This double change of the magnetic field of the core generates an impulse into a sense line which goes through the core (and, if the sense line bypasses the core, it will see no impulse).

2) In the case that a core shouldn't be activated because it is not currently the tested core, the process of inhibition of the activation of the core is described on the lower half of the figure. The set current (left of the figure) in one direction is sent into the common set/reset line, but a reset current in opposite direction is simultaneously sent into an inhibit line going through the core.
The set current and the reset current are of equal intensity, and, as they are opposed to each other, they are going to cancel each other; because of the reset current going through the inhibit line, the set current of the common set/reset line cannot change the magnetic field of the core, and thence no impulse will be generated by this core in a sense line passing through this core.
The reset current (right on the figure) is then sent into the common set/reset line, but, as the magnetic field has not been changed because of the inhibition, the core will not react to this reset.

In order to activate a single core, no current must be sent into the inhibit line(s) passing through this core, and, in all the other cores, there must be (at least) an inhibit line that a reset current is passing through.

(Note also that the fact that currents are sent into two wires must not be compared with the currents sent into two wires in the normal core memory: In the normal core memory, it is two half currents complementing each other, and here it is two full currents cancelling each other).

Therefore, the concept of the inhibit lines seems less obvious to use than the one of the activation lines, but it seems to work anyway. Yet this concept creates big problems as we are going to see.

Fig 16

I have colored with different colors the four inhibit lines which select or inhibit the cores.

Fig 17

You can see that each of these inhibit lines goes through two cores. The third activation line goes through the second and fourth cores. If a reset current is sent into this line only, the set current going through the common set/reset line will activate the first and third cores, for only the second and fourth are inhibited from changing the magnetic field of the core.

Fig 18

If we want only the first core to be activated, then reset currents must be sent both through the third and fourth inhibit lines. Notice that these lines both go through the fourth core; that means that two reset currents instead of one will be sent through this core.

Fig 19

The process of reading the bits programmed on the cores for the 16 sense lines is described in the demonstration. Reset currents are first sent into the third and fourth inhibit lines when the set current is sent into the common set/reset line so that only the first core is activated. As only the first sense line is going through the first core, neither the second sense line nor the 16th sense line (the other sense lines are not specified), only the first sense line has a 1 programmed on this core while the other sense lines have a 0 programmed on this core.

So, for the first core, we have the combination "10...0" (starting from the first sense line).

Fig 20

Then a reset current is sent through the second and fourth inhibit lines, causing the inhibition of all the cores save the second one, which is the currently tested one. As only the second sense line is going through the second core, it is the only one which will receive an impulse.

So, for the second core, we have the combination "01...0".

Fig 21

Then a reset current is sent through the first and third inhibit lines, causing the inhibition of all the cores save the third one, which is the currently tested one. As the second and 16th sense lines are going through the third core, it is these two which will get an impulse. So, for the third core, we have the combination "01...1".

Fig 22

Then a reset current is sent through the first and second inhibit lines, causing the inhibition of all the cores save the fourth one, which is the currently tested one. As only the first sense line is going through the fourth core, it is the only one which will get an impulse. So, for the fourth core, we have the combination "10...0".

Fig 23

So, by successively activating one core at a time, it is possible to read the bits which have been programmed on the sense wires by making them either go through a core (for a 1) or bypass a core (for a 0). With these 4 cores and 16 sense lines, it is possible to memorize 4*16 = 64 bits. Notice however that we have had to send two reset currents at each step of the process (and that there is a core which receives two reset currents instead of one).

Fig 24

Another solution would be to make each inhibit line go through all the cores save one, so through 3 cores in this simplified example.

– The first inhibit line goes through the second, third and fourth cores, but not the first one; so sending a reset current into it will inhibit the activation of all the cores save the first one.
– The second inhibit line goes through the first, third and fourth cores, but not the second one; so sending a reset current into it will inhibit the activation of all the cores save the second one.
– The third inhibit line goes through the first, second, and fourth cores, but not the third one; so sending a reset current into it will inhibit the activation of all the cores save the third one.
– The fourth inhibit line goes through the first, second, and third cores, but not the fourth one; so sending a reset current into it will inhibit the activation of all the cores save the fourth one.

Fig 25

So now we just have to send one single inhibit current to test each core... but we have to make pass through each core a number of inhibit wires equal to the number of cores minus one (3 in our example of 4 cores). We will therefore have to look for another solution.

Fig 26

Another solution is to make pass a single inhibit line through each core:

– The first inhibit line will go only through the first core and will only allow to inhibit the first core.
– The second inhibit line will go only through the second core and will only allow to inhibit the second core.

So, in this solution, only one inhibit line goes through a core, and it solves the number of inhibit lines going through a core.

Fig 27

But, when a core is to be activated, all the other cores must be inhibited, which means that reset currents must be sent into all the inhibit lines save the inhibit lines going through the currently tested core. Even if the management of the memory is made with separate units which they show in the schematics, that still makes three currents which must be sent to read a core – when one would have been enough if activate lines had been used instead of inhibit lines.

Fig 28

So, why not use the normal concept of "Activate wires" instead of "Inhibit wires”? In the concept of "Activate wires", only one Set current is sent into an activate line when a core is tested, and only one activate line goes through a core. No problem of multiple lines going through a core and no waste of energy.

This shows that using the concept of "Inhibit wires" to alternately activate the cores which are tested makes no sense, and that the concept of "Activate lines" is the only reasonable concept that can work. In fact, the designers could have activated the core which is to be tested the same way as in the conventional core memory. By sending half currents in lines and columns of a matrix of wires, so that the core which is tested is at the intersection of the line and column into which half currents are currently sent.

Fig 29

But the fact that they have illogically used "Inhibit lines" instead of "Activate lines" is not the only problem of the ROM card. This schematic shows how the impulse generated by the cores was read. There were commands to activate the reading of the impulses generated by the cores individually. In order to select the sense line which was to generate an impulse on the output coil (circled in blue), they were using line selection and module selection commands; for instance, in this schematic, the only sense line of the four which can generate its impulse into the coil is the one framed in light green, because it is the only one connected to both a selected line (represented in dark green) and a selected module (also represented in dark green); the three other ones, framed in light red, cannot generate their impulse into the coil, for they are connected either to a non-selected line (represented in dark red) or a non-selected module (also represented in dark red ), or even to both.

Fig 30

I offer some explanations about the way the sense current was transmitted to the coil.

– I call VR the reference voltage of 14 volts
– I call R the value of the resistors
– I call I1 the intensity which comes from the line selection.
– I call I2 the intensity which goes through the diode D4 (which comes from the right).
– I call V the voltage of the common point I have circled in red.

The intensity which goes to the module selection point is equal to the sum of I1 and I2.
So that V:

– Is equal to R*(I1+I2)
– Is also equal to VR-0.7-R*I1
– And also equal to VR-0.7-R*I2
(0.7 being the voltage between the ends of the diodes)

Therefore we have the two equations:
R*(I1+I2)=VR-0.7-R*I1
R*(I1+I2)=VR-0.7-R*I2
Solving these equations gives:
I2=(VR-0.7)/(3*R)

Fig 31

When the sense line generates a current I'll call i, this current also goes through the resistor which is connected to the module selection point.
So, now we have: V=R*(I1+i+I2)
And the equations become:
R*(I1+I2+i)=VR-0.7-R*I1
R*(I1+I2+i)=VR-0.7-R*I2

Solving this equation gives this result:
I2=(VR-0.7)/(3*R)-i/3
So this is a variation equal to i/3 relative to the previous value.

Fig 32

This means that only one third of the very weak impulse in the sense line comes to the coil. 48 selected sense wires may potentially have a current going through, and, as the current of the selected sense wire is divided by three before coming to the primary of the coil of the amplifier, it produces a current too weak to be amplified.

Fig 33

The impulse detected in the sense line is amplified to be used by the schematic of a circuit which is shown here. We have seen that the impulse in the coil is only one third of the impulse in the sense line. We are now are going to see that this very weak impulse was incorrectly amplified.

Fig 34

This amplifier uses two pairs of transistors; this special assembly is called a "push-pull"; it means that the first coupled pair of transistors (circled in green) amplifies the positive edge of the impulse (colored in green), and the second coupled pair of transistors (circled in blue) amplifies the other edge of the impulse (colored in blue).

Fig 35

I show here a simple amplifier made with a transistor. The signal to amplify is sent on the base of the transistor (the connection which is on the center of the transistor), and the amplified signal is obtained on the collector of the transistor.

Fig 36

On the first pair of the push-pull (transistors circled in green), the collector of the first transistor of the pair is connected on the base of the second transistor; it is the connection drawn in red. But in the second pair of the push-pull (transistors circled in blue), the collector of the first transistor should also be connected to the base of the second transistor… but this is not the case, the connection between the collector of the first blue transistor and the base of the second blue transistor is missing; I have circled the place at which this missing connection should be visible… and it is not present.

Moreover, there is no connection between the two transistors of the second pair of the push-pull, it means that the second edge of the sense impulse cannot be amplified.

This omission is clearly intended as a clue of the fakery.

Fig 37

Fig 37a

The missing connection between the base and the collector is certainly not accidental, as this ‘mistake' exists in two different schematics, one in a document dated 1966, and the other in a document dated 1972.

Fig 38

In an article published in January 1967, Albert L. Hopkins of MIT shows the schematic of the amplifier, and, on this schematic, the bug of the missing correction has been corrected; as the Hopkins article was published between the dates of the two documents in which the error exists, it shows that the argument that there might have been a decision about adding this connection or removing it does not hold. Hopkins corrected this mistake to attract attention to show that something was abnormal. Nevertheless, Hopkins left the error of the incorrectly-mounted output transistor.

Fig 39

With regard to the incorrectly-mounted output transistor, I initially thought that the strobe controlling the output was intended as an anomaly.

Fig 40

This would have been true on the prototype card, which had up to 64 sense wires passing through the cores. Indeed, as there are 16 bits to read simultaneously, that would make 64/16=4 sense wires per bit.

Fig 41

As the sense line selection is allowing the selection of one in four sense lines, it means that the selected sense line would have represented one bit of the 16-bit word to read.

Fig 42

And the diagram to read a bit of the 16-bit word would have looked like this. The sense line selection would have selected one of the four sense lines of the bit, the amplifier would have amplified it, and the output of the amplifier would directly have been a bit of the word.

For the prototype card, the strobe would indeed have been useless, and its presence an anomaly.

Fig 43

But, in the final core rope modules, it is not 64, but 192 wires which could pass through a core, three times more than for the prototype card. That could make 192/16 = 12 sense lines for a bit.

Fig 44

It means that what the sense line selection was selecting was not representing a bit, but one in three possibilities for the bit. For the sense line selection to select a sense line directly corresponding to a bit, it should have been able to select one in 12 lines.

Fig 45

Furthermore, as I have previously demonstrated, the sense line selection is reducing the current of the selected sense line to a third before it came to the amplifier.

Fig 46

For the final core rope module, the diagram for the acquisition of a bit of the 16-bit word would have looked like this. There would have been three sense line selection modules; each of these sense line selection modules would have selected one in 4 sense lines; each output of a sense line selection module would have come into an amplifier which would have amplified it, but only one amplifier's output would have been taken into account to represent the final bit, and the two other amplifier's outputs ignored, although they also were amplifying a selected sense line.

Fig 47

So, for the final core cope module, the strobe finally has a meaning: it is allowing it to specify if this amplifier's output would be taken into account to represent the read bit, or ignored. But if the strobe is not an anomaly, the output transistor is still incorrectly connected.

It is in fact upside down.

Fig 48

When a NPN transistor (emitter's arrow oriented outward) is used to validate or invalidate a signal by controlling its base, its emitter is connected to a steady reference, generally the ground; here, it is not the case, for the emitter is connected to the amplifier's stage output, of which the voltage changes when it amplifies a pulse.

Fig 49

And, when the transistor's base is grounded, and the amplifier's stage is not amplifying a pulse, it would have a negative voltage relative to the emitter connected to the +14V, and it is not good for the transistor.

Fig 50

This is the way the output transistor should have been connected, with its emitter connected to the ground.

Fig 51

When the base of the transistor is activated, the output transistor would conduct, forcing the collector to the ground, and the final amplifier's output would then not follow the output of the amplifier stage, which means that it would not be selected to output the bit.

Fig 52

And, when the base is grounded, the transistor's collector would then follow the output of the amplifier stage, which means that it would then be selected to output the bit.

Fig 53

This simplified schematic shows how the three amplifiers would be connected, so that only the output of one would be selected to output the bit. The outputs of the amplifiers would be inputted to a NOR gate; a NOR gate outputs a 1 when all its inputs are 0, and a 0 otherwise. For two of the amplifiers, the ones which are not selected, the strobes would be activated, which would force their outputs to 0, and, for the third one, the one which is selected, the strobe would be grounded, allowing its output to follow the output of the amplifier's stage; when there is no pulse, this output would be 1, forcing the bit output to 0.

Fig 54

And, when a pulse would occur, the output of the amplifier's stage would be pulled down by the pulse, and the amplifier's output would become 0, which would force the output bit to 1.

Fig 55

So, if the missing connection between the base and the collector in the amplifier's stage is restored, and if the output transistor is correctly connected, does it then mean that this amplifier will work correctly?

In fact there is yet another problem, though it is less visible.

Fig 56

This is the schematic of the selection of a sense line and its amplification in a patent of core rope memory of a printer, which memorizes the dot matrix for a character to be printed. The cores, which represent lines of the dot matrix, are successively activated, and the sense lines, representing the columns of the dot matrix, are successively selected and amplified to print a dot of the character. The patent states regarding this amplifier that it does not only amplify the pulse, it also stretches it.

Fig 57

A pulse stretcher is an interface that allows it to make a pulse longer in order to exploit it more easily, to leave time to read it.

Fig 58

The part framed in red on the printer's bit amplifier is called an RC circuit (with a resistor and a capacitor), and allows it to convert the pulse on the secondary of the transformer into a temporary permanent current, which then can be read by the reading logic. After the bit is read, the state of the input I have circled in blue is changed in order to discharge the capacitor, and allow the reading of the next bit.

This circuit is absent in the AGC's bit amplifier, which means that the pulse is not memorized on the secondary of the transformer, and so all the transformer does is to transmit the pulse to the amplifier without memorizing it, and, as such, it is useless.

If the pulse is not memorized, it cannot be read by the reading logic, for it passes too fast.

Fig 59

Why would the sense pulse need to be stretched? For the bit interface to correctly acquire the bit from the sense pulse, there are two conditions:
1) The sense pulse must already be activated when it is read.
2) The sense pulse must still be activated when it is read.
If the bit was acquired at exactly the same time as the core is activated, it would not be acquired correctly for the sense pulse would not still be present.

Fig 60

That's why the process of the bit reading is made in three steps sequenced by timing:
1) Activation of the core
2) reading of the sense pulse
3) Reset

Fig 61

However, there is no guarantee that the pulse will still be active when the bit is acquired at the second step, in which case it would be read 0 whereas the pulse actually occurred.

Fig 62

That's why the pulse is stretched by the amplifier, so that the amplified pulse is certain to be present when it is acquired at the second step. The reset at the third step cuts the stretched pulse, moreover resetting the core.

Fig 63

How then would the interface of a bit have worked, supposing all the flaws I have highlighted allowed it to work? There are 12 possible sense lines for a bit, but, for a given address, only one of these sense lines is to be taken into account. Suppose the first one has to output the corresponding bit.

The first sense line selection module must select the first sense line; as the selection lines are inputted into the three selection modules, the two other selection modules also select the first line, but in fact it is not relevant for their amplified outputs will not be taken into account. The strobes are programmed so that it is the output of the first amplifier which is taken into account; the output bit corresponds to the first of the 12 sense lines associated with this bit.

Fig 64

Let us now suppose that it is the second of the 12 sense lines associated with the bit which is to represent the bit. The first sense line selection module must now select its second input, and the strobes are still programmed so that it is the output of the first amplifier which is taken into account; the output bit corresponds to the second of the 12 sense lines associated with the bit.

Fig 64

Let's now suppose that it is the fifth of the 12 sense lines associated with the bit which is to represent the bit. The second sense line selection module must select its first input, and the strobes must be programmed so that it is the output of the second amplifier which is taken into account; the output bit corresponds to the fifth of the 12 sense lines associated with the bit.

Fig 65

Now let us suppose that it is the sixth of the 12 sense lines associated wit the bit which is to represent the bit. The second sense line selection module must select its second input, and the strobes must be programmed so that it is the output of the second amplifier which is taken into account; the output bit corresponds to the sixth of the 12 sense lines associated with the bit.

Fig 66

There is no need to provide any more examples: selecting a sense line is done by making a double selection: selecting a sense line selection's input, and selecting an amplifier's output. But, is this the best way for a bit's interface to work (ignoring the flaws of the amplifiers)?

Fiog 67

I have only represented two commands to control the sense line selection block, for there only are four possible combinations to select one in four sense lines. It means that each input is inputted twice in the control of the selection interface; once non inverted, and once inverted.

Fig 68

It would be possible to control the sense line selection interface with four independent commands. It would allow it to select several sense lines at the sense time, which does not offer the least interest, but it would also allow it to select none of them, which means that no current would go from the sense line selection interface to the corresponding amplifier, and this is more interesting. This might be interesting for there would be no reason that a current would run through a sense line, and would be amplified, if the amplifier's output is not taken into account to generate the bit. But, in this case, it would mean that the strobes would be unnecessary.

Fig 69

Indeed, since the corresponding amplifiers receive no pulse, their outputs will remain to 1, which means that the outputs of the amplifiers can directly be connected to a NAND gate, without being controlled by a strobe. The amplifier that receives a pulse will amplify it and will output a 0, which will force the NAND's output to a 1.
And, if the selected sense wire gets no pulse (i.e. does not pass through the activated core) the corresponding amplifier will output a 1, which will generate a 0 on the NAND's output, since the outputs of the other amplifiers remain to 1, as they receive no pulse, the output of their sense line selection interface being disabled.

Fig 70

In short, it means that, if the sense line selection interfaces could be controlled so that they would select no sense line at all, the strobe which controls the amplifier's output would become useless, and the amplifier could be simplified as I show.

Fih 71

But the strobe which controls the amplifier's output is here, and its presence proves that the engineers had excluded the possibility that the sense line selection interfaces could be controlled to select no sense line at all.

Fig 72

Let's now consider again the selection and amplification of the sense lines of the printer's interface (and we can assume it worked, it had not gone on the Moon and had no reason to cheat). Look how the selection was done: the selection commands (C1 to C5) were inputted on the middle of the resistor’s bridges, and the sense lines were arriving on the extremities of these resistor’s bridges; they were connected to the primary of a transformer through diodes; a sense line was selected by activating its command line, while the other command lines were grounded; only the sense line of which the command line was activated had a current running through it, provided that it was going through the currently activated core, and it is its current which was running through the primary of the transformer, without being reduced, amplified and stretched by the amplifier which follows.

Fig 73

This printer's interface shows how the selection of the sense lines should have been made: There should have been a unique transformer, and as many resistor’s bridges as sense lines associated to the bit (12), as many command lines as sense lines to select; only one command would have been activated at a time, allowing a current to run through its associated sense line when it was passing through the activated core, and the current of the selected sense line would have run through the primary of the transformer without reduction; all the other 11 sense lines would not have had a current running through them, for their command lines would have been grounded. Notice the capacitor connected on the secondary of the transformer, which allows it to maintain the pulse after it has disappeared on the primary, and which leaves the time to read it – this capacitor is missing in the drawings of the memory of the Apollo AGC.

Fig 74

For instance, if it is the first sense line which is to be read for the bit, only the first command line would be activated, and all the other ones grounded; the current of the first sense line would run through the transformer entirely, without reduction and would be correctly amplified and stretched by the unique amplifier of the bit, and the unique amplifier for the bit would have output a memorized bit, without a strobe being necessary.

Fig 75

And, likewise, if it is the second sense line which is to be read for the bit, only the second command line would be activated, and all the other ones grounded; the current of the second sense line would entirely run through the transformer, and would be correctly amplified and stretched by the unique amplifier of the bit.

Fig 76

So, this is definitively the way the bit's interface should have worked, provided that we keep the logic of using sense lines for programming the bits.

Fig 77

On one side, we have three sense line selection modules, reducing to a third the current of the selected sense line, and allowing three currents to run through three selected sense lines, three amplifiers, consuming currents, incorrectly amplifying the pulse, not stretching it, and incorrectly strobed. Then on the other side, we have an unique selected sense line, which is the only one which has a current passing through, which is not reduced before coming to the amplifier, which is correctly amplified and stretched by an unique amplifier which directly outputs the bit.

There is no need to tell you which is the best of the two – you are be able to figure that one out!

Fig 78

And selecting the sense line for the bit does not require more bits from the address bus for the improved interface than for the AGC interface. Indeed, selecting the command among the 12 possible ones for the improved interface would be made with a circuit called "1 of N decoder”; it is a circuit which accepts a combination of n binary inputs and outputs 2^n outputs (two n times multiplied by itself), of which only one is activated at a time, which corresponds to the binary combination of the inputs; the displayed example shows how to validate one of the four outputs according to the binary combination of the two inputs.

Fig 79

Rather than showing a complete schematic for a decoder having 4 inputs and 16 outputs, which would be a little overloaded to be legible, I show here an animation which shows how each gate of the decoder would be connected to the four inputs. This decoder would allow the selection of one of the 12 commands of the improved bit interface from a 4 bit address. It is not necessary to repeat this decoder for the 16 bits, the same decoder could be used for all the bit interfaces.

Fig 80

And concerning the bit interface of the AGC, a two bit address would be needed to select one sense line out of four, and another two bit address would be needed to select one of the three amplifier's outputs, which would also make a four bit address at total.

Fig 81

It means that the improved bit interface does not mean more bits to be controlled from the address bus than the AGC bit interface.

Fig 82

Moreover, the inhibit lines were not even used correctly; the way they were used meant there were two inhibit currents passing through a core.

Fig 83

If they had been used correctly, then only one inhibit line would have passed through each core, and would have been activated to inhibit this core, as was the case in the printer's memory, which actually works.

Fig 89

Furthermore, the fact that the inhibition process is incorrect (because of two activated inhibit lines passing through a core), using the inhibit wires as was made in the AGC also implies that the inhibit wires also had to be woven to alternately go through or bypass the cores. And we are going to see that it complicates the weaving test.

Fig 90

Let's consider the sense wire 2, indicated with a blue arrow. This wire bypasses the first core (when it is correctly woven), because a 0 is programmed for this sense wire on the first core. So, when a current is sent into the common set line (wire colored in green), and counter-currents are sent into the third and fourth inhibit lines, as these inhibit lines pass through all the cores save the first one, they will prevent all the cores from being activated by the current of the common set line, save the first core which will thus be the only one to be activated. If the sense line 2 bypasses the first core, like it should, it will then show no current, showing that a 0 is programmed for this sense line on the first core; the detection of no current in the sense wire 2 will show it has been correctly woven.

Fig 91

Now, let's consider this situation. The sense wire 2 (indicated with a blue arrow), instead of bypassing the first core, passes through it instead, because a gentle weaving hand has made a mistake. The result is that, when the first core is activated (by sending a current into the common set line, and counter-currents into the third and fourth inhibit lines), it will show a current, when it should not. The engineers will then deduce that a gentle weaving hand has made this sense wire pass through the first core, when it should have bypassed it, and will have the faulty sense wire removed and woven again.

Fig 92

Let is consider this situation instead. The sense wire 2 (indicated with a blue arrow) has been correctly woven, and bypasses the first core like it should. But the third inhibit line (pointed by a pink arrow), instead of passing through the second core, bypasses it. The result is that when a current is sent through the common set line, and counter-currents through the third and fourth inhibit lines, there will be no activated inhibit line passing through the second core, and thence the second core will be activated in the same time as the first core, when it should not.

As the sense wire 2 passes through the second core, and the second core is incorrectly activated, the sense wire 2 will be activated, not because the first core is activated, but because the second one is. If the engineers think that the inhibit wires are correctly woven, they will deduce that the sense wire 2 has been incorrectly woven, that it passes through the first core when it should bypass it, and will have it rewoven, whereas it is correctly woven in fact, for it does bypass the first core, exactly as it should.
So reweaving the sense wire will not solve the situation.

Fig 93

So, does this mean that, if the bit interface had looked like this, it could have worked normally, and that it is the way it should have been conceived?

Fig 94

There is however a big difference with the printer's memory we have seen. In this printer's memory, the selection is made between all the sense lines which can pass through the cores; it means that there will never be more than one sense line that a current is passing through.

Fig 95

In this bit's interface, there is only one current passing through the selected sense line of the bit, but there are 16 bits for the word to be read, which means that there are 15 other currents which can run through the 15 other selected sense lines corresponding to the 15 other bits (provided of course that they go through the activated core, which can happen). So, if this interface is used, it still means that there may be 16 currents running through selected sense lines (in the original interface of the AGC, it is 48), and 16 is too much, it implies a consistent reduction of current running into each of these selected sense lines (provided of course that they all go through the activated core, which may happen).

This means that although this interface is much more performant than the one of the AGC, it still has a severe deficiency for it to work correctly.

Fig 96

That's why the core rope memories of computers other than the AGC, like the one of the UNIVAC lower image), although they show a similarity with the core rope memory of the AGC, the memories work in a completely different way.

Fig 97

Indeed, in these memories, the lines, which pass through or bypass the cores, are not sense lines, but are drive lines instead, and that changes everything. In these memories, the cores have an unique sense wire. In the patent of a core rope memory for a computer the text associated with this figure reads as follows:

"When the magnetic easy axis of the magnetic thin-film wire 1 is in the circumferential direction thereof, the magnetic thin-film wires 1 are used as information lines (which function doubly as digit lines and sense lines), and the conductor wires 2 are used as word drive lines."

In the memory of the AGC, only one core is activated at a time, and currents can go through several sense lines. Additionally, in the core rope memories which actually work, only one drive line is activated at a time, and several cores may be activated by this drive line at a time, generating a current into each of their unique sense lines.

Fig 98

Instead of being read on a unique core, the bits are read on several cores. With the same number of drive lines as sense lines, and the same number of cores, these memories can memorize the same number of bits, for, the same that a sense line programs a bit by passing through or bypassing a core, a drive line also programs a bit by passing through or bypassing a core.

Fig 99

So, if the core rope memory of the AGC was working according on the same principle as the core rope memories of other computers, which are proven to work, the schematics would be changed as I show here; the lines passing through or bypassing the cores would be labeled as drive lines, and not sense lines, and there would be no inhibit lines, which means that the latter would not have to be woven in the cores, unlike in the original memory of the AGC.

Fig 100

How the memory should have worked

The first drive line passes through the first and fourth cores, which means that when it is activated, the first and fourth cores are activated, and their sense lines when detecting a current, would correspond to the 4-bit word 1001.

Fig 101

The second drive line passes through the second and third cores, which means that when it is activated, the second and third cores are activated, and their sense lines when detecting a current, would correspond to the 4-bit word 0110.

Fig 102

Finally, the third drive line passes through the third core, which means that, when it is activated, the third core is activated, and its sense line detecting a current, would correspond to the 4-bit word 0010.

Fig 103

This demonstration is with four cores, but the number of cores for reading a 16 bits word would in fact be extended to 16, in order to read the sixteen bits of the word. So it is clear that this way of working is much better:
1) No need for inhibit lines
2) Only one current running into a sense line, which means that the current running through it would be consistent enough to be amplified.

Fig 104

So, this interface is much better than...

Fig 105

… this one, which itself is much better than...

Fig 106

… the one which had been conceived for the AGC. This interface is so bad, it has so many handicaps, that it had absolutely no chance of working. Not at all. Moreover, the design engineers must have known this, as they obviously wanted it to be extremely bad and for it not to work.

Fig 107

This is the simplified schematic of the erasable memory. The brick inside the loops of current represents the arrays of cores. If no core rope memory has ever been used apart for the AGC (at least in the way it was designed for Apollo) – which is certainly not the case of the normal erasable core memory that can actually work. Therefore, if the ROM memory of Apollo computer couldn't work, could we at least have expected that the RAM memory would have worked?

No. The engineers even managed to make the erasable memory unable to work as well!

Fig 108

 

I have represented in red the path of the write current; the current turns clockwise in the loop; this makes it go up in the block of the cores.

Fig 109

And I have represented in blue the path of the read current (the sense line); the current turns also clockwise, but, as it is on the left of the write loop, this makes it go down in the block of the cores.

Fig 110

Now, what's abnormal is that the write current loop and the read current loop have a common part: it is the same wire which allows it to both change the magnetic field of a core and also to sense the impulse which is generated by the change of magnetic field of a core.

Fig 111

This is absolutely impossible: The wire that allows it to generate the change of magnetic field of the core by sending a current into it cannot also get the impulse generated by the change of the magnetic field; this change of magnetic field has to be detected in another wire, called a sense wire; the wire generating the impulse and the one reading it cannot be the same. Not under any circumstances.

Fig 112

And what makes it all the more absurd is that the current of the write loop and the current of the read loop go in converse direction in their common part!

Fig 113

You might have thought that it was incoherent enough for the engineer fakers to be satisfied? Oh no, they had to add even more. This is the schematic of the regulated pulse current driver which allows it to read the sense pulse.

Fig 114

This interface contains two transistors (T2, T3) mounted in current regulator. The current regulation is based on the fact that, when a current runs through a diode, it generates a difference of voltage of 0.7 volts on the ends of the diode. When there is a pulse on the base of T1, T1 gets activated and the current can pass between the collector and the emitter of T1. Because of the double diode connected to the base of T2, the voltage on the base of T2 is then equal to 14-1.4 volts (2x0.7=1.4); the voltage on the emitter of the PNP transistor T2 is equal to the voltage on the base of T2 plus 0.7 volts, so 14-0.7 volts; this would generate a regulated current of 0.7/R through the resistor R.

If T2 is activated, the current can go through its emitter to its collector, and also go through the double diode connected to the base of T3; the voltage on the base of T3 is then equal to 1.4 volts (2x0.7 volts). If the transistor T2 is activated, the voltages on its emitter and its collector should be equal, but the double diodes D1&D2 force the voltage of the emitter to 13.3 volts, and the doubles diodes D3&D4 force the voltage of the collector to 1.4 volts! It can't work, this interface is departing from an accepted standard.

So, as incredible as it may seem, according to NASA's published documentation, neither the ROM memory nor the RAM memory of the Apollo Guidance Computer could have ever worked.

Xavier Pascal

Aulis Online, May, 2019


About the author

Xavier Pascal is a computer engineer specialising in real-time systems. He constructed a number of electronic interfaces with digital electronics in the nineteen seventies and eighties. He states that he is sufficiently qualified to read and to understand the technical documentation of the Apollo Guidance Computer, and his observations of the (intentional) flaws in the documents form the basis of his article.


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